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873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 1 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary g eneral d escription the ICS873034 is a low skew, high perfor- mance differential-to-2.5v, 3.3v lvp ecl/ecl clock generator and a member of the hiperclocks? family of high performance clock solutions from ics. the ICS873034 is characterized to operate from either a 2.5v or a 3.3v power supply. guaranteed output and part-to-part skew characteristics make the ICS873034 ideal for those clock distribution applications demanding well defined performance and repeatability. f eatures ? 3 differential 2.5v, 3.3v lvpecl / ecl output ? 1 differential pclk, npclk input pair ? pclk, npclk pair can accept the following differential input levels: lvpecl, lvds, cml, sstl ? input frequency: 3.5ghz ? translates any single ended input signal to 3.3v lvpecl levels with resistor bias on npclk input ? lvpecl mode operating voltage supply range: v cc = 2.375v to 3.8v, v ee = 0v ? ecl mode operating voltage supply range: v cc = 0v, v ee = -3.8v to -2.375v ? -40c to 85c ambient operating temperature ? pin compatible with mc100lvep34 b lock d iagram p in a ssignment ICS873034 16-lead soic, 300mil 7.5mm x 10.3mm x 2.3mm package body m package top view hiperclocks? ics ICS873034 16-lead tssop 4.4mm x 3.0mm x 0.92mm package body g package top view q0 nq0 v cc q1 nq1 v cc q2 nq2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v cc nen nc pclk npclk v bb mr v ee pclk npclk q0 nq0 q1 nq1 q2 nq2 nen d q le v bb mr 2 r 4 r 8 r the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice.
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 2 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 10 q n , 0 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 6 1 , 6 , 3v c c r e w o p. s n i p y l p p u s r e w o p 5 , 41 q n , 1 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8 , 72 q n , 2 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 9v e e r e w o p. n i p y l p p u s e v i t a g e n 0 1r mt u p n in w o d l l u p t e s e r e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a o g o t x q n s t u p t u o d e t r e v n i e h t d n a w o l o g o t x q s t u p t u o e u r t e h t g n i s u a c . d e l b a n e e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 1v b b t u p t u o. e g a t l o v s a i b 2 1k l c p nt u p n i / p u l l u p n w o d l l u p v o t s t l u a f e d . t u p n i k c o l c c c . s l e v e l e c a f r e t n i l c e p v l . n e p o t f e l n e h w ) 6 6 . ( 2 / 3 1k l c pt u p n in w o d l l u p . s l e v e l e c a f r e t n i l c e p v l . g n i t a o l f t f e l n e h w w o l t l u a f e d . t u p n i k c o l c 4 1c nd e s u n u. t c e n n o c o n 5 1n e nt u p n in w o d l l u p . t u p n i k c o l c w o l l o f s t u p t u o k c o l c , w o l n e h w . e l b a n e k c o l c g n i z i n o r h c n y s . h g i h d e c r o f e r a s t u p t u o q n , w o l d e c r o f e r a s t u p t u o q , h g i h n e h w . s l e v e l e c a f r e t n i s o m c v l / l t t v l : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 3. t ruth t able s t u p n i n o i t c n u f k l c pn e nr m zll e d i v i d z zhl 2 q : 0 q d l o h xx h 2 q : 0 q t e s e r n o i t s i s n a r t h g i h o t w o l = z n o i t s i s n a r t w o l o t h g i h = z z l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 5 7k ? r n w o d l l u p r o t s i s e r p u l l u p t u p n i 5 . 7 3k ?
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 3 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary t able 4a. p ower s upply dc c haracteristics , v cc = 2.375v to 3.8v; v ee = 0v l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 5 7 3 . 23 . 38 . 3v i e e t n e r r u c y l p p u s r e w o p 0 4a m a bsolute m aximum r atings t able 4b. lvpecl dc c haracteristics , v cc = 3.3v; v ee = 0v note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifi- cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect product reliability. supply voltage, v cc 4.6v (lvpecl mode, v ee = 0) negative supply voltage, v ee -4.6v (ecl mode, v cc = 0) inputs, v i (lvpecl mode) -0.5v to v cc + 0.5v inputs, v i (ecl mode) 0.5v to v ee - 0.5v outputs, i o continuous current 50ma surge current 100ma v bb sink/source, i bb 0.5ma operating temperature range , ta -40c to +85c storage temperature, t stg -65c to 150c package thermal impedance, ja 90c/w (0 lfpm) (junction-to-ambient) for 16 lead soic package thermal impedance, ja 89c/w (0 lfpm) (junction-to-ambient) for 16 lead tssop l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 7 2 . 25 9 2 . 23 3 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 4 5 . 12 5 . 15 3 5 . 1v v h i ) d e d n e - e l g n i s ( e g a t l o v h g i h t u p n i 5 7 0 . 26 3 . 25 7 0 . 26 3 . 25 7 0 . 26 3 . 2v v l i ) d e d n e - e l g n i s ( e g a t l o v w o l t u p n i 3 4 . 15 6 7 . 13 4 . 15 6 7 . 13 4 . 15 6 7 . 1v v b b e c n e r e f e r e g a t l o v t u p t u o 6 8 . 18 9 . 16 8 . 18 9 . 16 8 . 18 9 . 1v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 0 80 0 80 0 8v v r m c e g a t l o v h g i h t u p n i 3 , 2 e t o n ; e g n a r e d o m n o m m o c v i h i t u p n i t n e r r u c h g i h k l c p n , k l c p 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l k l c p n , k l c p 0 1 -0 1 -0 1 -a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t c c . v 2 - v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . v s i k l c p n , k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 3 e t o n c c . v 3 . 0 +
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 4 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary t able 4d. ecl dc c haracteristics , v cc = 0v; v ee = -3.8v to -2.375v t able 4c. lvpecl dc c haracteristics , v cc = 2.5v; v ee = 0v l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o ; e g a t l o v h g i h t u p t u o 1 e t o n 5 2 0 . 1 -5 0 0 . 1 -5 0 0 . 1 -v v l o ; e g a t l o v w o l t u p t u o 1 e t o n 5 5 7 . 1 -8 7 . 1 -5 6 7 . 1 -v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 0 80 0 80 0 8v v r m c e g a t l o v h g i h t u p n i ; e g n a r e d o m n o m m o c 3 , 2 e t o n v e e v 2 . 1 +0v e e v 2 . 1 +0v e e v 2 . 1 +0v i h i t u p n i t n e r r u c h g i h , k l c p k l c p n 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l , k l c p k l c p n 0 1 -0 1 -0 1 -a 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t c c . v 2 - v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . v s i k l c p n , k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 3 e t o n c c . v 3 . 0 + l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 7 4 . 15 9 4 . 13 5 . 1v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 4 7 . 02 7 . 05 3 7 . 0v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 7 2 . 16 5 . 15 7 2 . 16 5 . 15 7 2 . 16 5 . 1v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 3 6 . 05 6 9 . 03 6 . 05 6 9 . 03 6 . 05 6 9 . 0v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 0 80 0 80 0 8 m v v r m c e g a t l o v h g i h t u p n i 3 , 2 e t o n ; e g n a r e d o m n o m m o c 2 . 12 . 12 . 1v i h i t u p n i t n e r r u c h g i h k l c p n , k l c p 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l k l c p n , k l c p 0 1 -0 1 -0 1 -a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t c c . v 2 - v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . v s i k l c p n , k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 3 e t o n c c . v 3 . 0 +
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 5 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary t able 5. ac c haracteristics , v cc = 0v; v ee = -3.8v to -2.375v or v cc = 2.375v to 3.8v; v ee = 0v l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m f x a m y c n e u q e r f t u p n i5 . 35 . 35 . 3z h g t d p 1 e t o n ; y a l e d n o i t a g a p o r p0 3 50 6 50 1 6s p t r r y r e v o c e r t e s e r / t e s0 2 30 2 30 2 3s p t s e m i t p u t e sn e n0 50 50 5s p t h e m i t d l o hn e n0 0 10 0 10 0 1s p t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 7 10 8 10 0 2s p c d oe l c y c y t u d t u p t u o0 50 50 5% f t a d e r u s a e m e r a s r e t e m a r a p l l a . d e t o n e s i w r e h t o s s e l n u , z h g 1 . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 6 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary p arameter m easurement i nformation o utput l oad ac t est c ircuit d ifferential i nput l evel p ropagation d elay s etup and h old t ime v cmr cross points v pp v ee npclk v cc pclk scope qx nqx lvpecl 2v -0.375v to -1.8v clock outputs 20% 80% 80% 20% t r t f v swing t pd npclk q0:q2 nq0:nq2 pclk v cc v ee t hold t set-up npclk pclk nen o utput r ise /f all t ime o utput d uty c ycle /p ulse w idth /p eriod pulse width t period t pw t period odc = q0:q2 nq0:nq2
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 7 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary a pplication i nformation f igure 2a. s ingle e nded lvcmos s ignal d riving d ifferential i nput figure 2a shows an example of the differential input that can be wired to accept single ended lvcmos levels. the reference voltage level v bb generated from the device is connected to w iring the d ifferential i nput to a ccept s ingle e nded lvcmos l evels the negative input. the c1 capacitor should be located as close as possible to the input pin. f igure 2b. s ingle e nded lvpecl s ignal d riving d ifferential i nput figure 2b shows an example of the differential input that can be wired to accept single ended lvpecl levels. the reference voltage level v bb generated from the device is connected to the negative input. w iring the d ifferential i nput to a ccept s ingle e nded lvpecl l evels vcc r2 1k v_ref c1 0.1u r1 1k single ended clock input pclk npclk pclk npclk vbb c1 0.1u clk_in vcc
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 8 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for 3.3v lvpecl o utputs f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 9 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary t ermination for 2.5v lvpecl o utput figure 4a and figure 4b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminat- ing 50 ? to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 4b can be eliminated and the termination is shown in figure 4c. f igure 4c. 2.5v lvpecl t ermination e xample f igure 4b. 2.5v lvpecl d river t ermination e xample f igure 4a. 2.5v lvpecl d river t ermination e xample r2 62.5 zo = 50 ohm r1 250 + - 2.5v 2,5v lvpecl driv er r4 62.5 r3 250 zo = 50 ohm 2.5v vcc=2.5v r1 50 r3 18 zo = 50 ohm zo = 50 ohm + - 2,5v lvpecl driv er vcc=2.5v 2.5v r2 50 2,5v lvpecl driv er vcc=2.5v r1 50 r2 50 2.5v zo = 50 ohm zo = 50 ohm + -
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 10 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary lvpecl c lock i nput i nterface the pclk /npclk accepts lv pecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 5a to 5f show interface examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver ter- mination requirements. f igure 5a. h i p er c lock s pclk/npclk i nput d riven by an o pen c ollector cml d river f igure 5b. h i p er c lock s pclk/npclk i nput d riven by a b uilt -i n p ullup cml d river f igure 5c. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river f igure 5f. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvds d river pclk/npclk 2.5v zo = 60 ohm sstl hiperclocks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v f igure 5e. h i p er c lock s pclk/npclk i nput d riven by an sstl d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm f igure 5d. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river with ac c ouple 3.3v 3.3v cml built-in pullup r1 100 pclk npclk hiperclocks pclk/npclk zo = 50 ohm zo = 50 ohm r2 50 zo = 50 ohm c1 r1 50 c2 pclk/npclk r5 100 - 200 zo = 50 ohm r6 100 - 200 pclk npclk vbb 3.3v lvpecl 3.3v 3.3v lvds 3.3v zo = 50 ohm 3.3v pclk npclk vbb r2 1k c2 r1 1k r5 100 c1 pclk/npclk zo = 50 ohm
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 11 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary a pplication s chematic e xample figure 1 shows an example of ICS873034 application schematic. in this example, the device is operated at v cc =3.3v. the decoupling capacitor should be located as close as possible to the power pin. the input is driven by a 3.3v lvpecl driver. r8 50 zo = 50 ohm (u1-3) r9 50 r2 82.5 3.3v zo = 50 ohm r10 50 r5 50 lvpecl r6 50 c1 0.1uf zo = 50 ohm zo = 50 ohm optional y-termination u1 ICS873034 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 q0 nq0 vcc q1 nq1 vcc q2 nq2 vee mr vbb nclk clk nc nen vcc r1 133 c2 0.1uf + - 3.3v r4 82.5 (u1-16) zo = 50 ohm r7 50 r3 133 c3 0.1uf zo = 50 ohm + - 3.3v (u1-6) 3.3v for the lvpecl output drivers, only two terminations examples are shown in this schematic. more termination approaches are shown in the lvpecl termination application note. f igure 6. ICS873034 a pplication s chematic e xample
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 12 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS873034. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS873034 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.8v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.8v * 40ma = 152mw ? power (outputs) max = 27.83mw/loaded output pair if all outputs are loaded, the total power is 3 * 27.83mw = 83.5mw total power _max (3.8, with all outputs switching) = 152mw + 83.5mw = 235.5mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature i n order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 82c/w per table 6a below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.236w * 82c/w = 104.4c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 6a. t hermal r esistance ja for 16- pin soic, f orced c onvection t able 6b. t hermal r esistance ja for 16- pin tssop, f orced c onvection ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 90c/w 82c/w 78c/w ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 137.1c/w 118.2c/w 106.8c/w multi-layer pcb, jedec standard test boards 89.0c/w 81.8c/w 78.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 13 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 7. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc - 2v. for logic high, v out = v oh_max = v cc_max ? 1.005v (v cc_max - v oh_max ) = 1.005 for logic low, v out = v ol_max = v cc_max ? 1.78v (v cc_max - v ol_max ) = 1.78v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc_max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 1.005v)/50 ? ] * 1.005v = 20mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc_max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.78v)/50 ? ] * 1.78v = 7.83mw total power dissipation per output pair = pd_h + pd_l = 27.83mw f igure 7. lvpecl d river c ircuit and t ermination vout q1 vcc - 2v rl 50 vcc
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 14 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary r eliability i nformation t ransistor c ount the transistor count for ICS873034 is: 280 t able 7a. ja vs . a ir f low t able for 16 l ead soic t able 7b. ja vs . a ir f low t able for 16 l ead tssop ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 90c/w 82c/w 78c/w ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 137.1c/w 118.2c/w 106.8c/w multi-layer pcb, jedec standard test boards 89.0c/w 81.8c/w 78.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 15 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary p ackage o utline - g s uffix for 16 l ead tssop t able 8b. p ackage d imensions l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n6 1 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 40 1 . 5 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0 p ackage o utline - m s uffix for 16 l ead soic t able 8a. p ackage d imensions l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n6 1 a- -5 6 . 2 1 a0 1 . 0- - 2 a5 0 . 25 5 . 2 b3 3 . 01 5 . 0 c8 1 . 02 3 . 0 d0 1 . 0 10 5 . 0 1 e0 4 . 70 6 . 7 ec i s a b 7 2 . 1 h0 0 . 0 15 6 . 0 1 h5 2 . 05 7 . 0 l0 4 . 07 2 . 1 0 8 reference document: jedec publication 95, ms-012
873034am www.icst.com/products/hiperclocks.html rev. a august 30, 2004 16 integrated circuit systems, inc. ICS873034 l ow s kew , 2, 4, 8 d ifferential - to - 2.5v, 3.3v lvpecl/ecl c lock g enerator preliminary t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extr aordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t m a 4 3 0 3 7 8 s c im a 4 3 0 3 7 8 s c ic i o s d a e l 6 1e b u t r e p 6 4c 0 7 o t c 0 t m a 4 3 0 3 7 8 s c im a 4 3 0 3 7 8 s c il e e r d n a e p a t n o c i o s d a e l 6 10 0 0 1c 0 7 o t c 0 g a 4 3 0 3 7 8 s c ig a 4 3 0 3 7 8 s c ip o s s t d a e l 6 1e b u t r e p 4 9c 0 7 o t c 0 t g a 4 3 0 3 7 8 s c ig a 4 3 0 3 7 8 s c il e e r d n a e p a t n o p o s s t d a e l 6 10 0 5 2c 0 7 o t c 0 the aforementioned trademark, hiperclocks? is a trademark of integrated circuit systems, inc. or its subsidiaries in the unite d states and/or other countries.

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